Fighting stringy chips on PEEK implants in the cleanroom was wrecking our sterile workflow; switching to a razor‑sharp uncoated carbide with a tiny hone and nudging SFM up gave me clean chip break and a tidier enclosure for bag-out. Anyone getting burr-free slotting on Ti-6Al-4V that still passivates nicely without extra hand work?
I’ve had good results slotting Ti‑6Al‑4V with a sharp 3‑flute TiAlN and through‑tool coolant: leave about 0.002" per side, then take a climb‑only high‑chip‑load “skim pass” to wipe the burr while keeping surfaces clean for citric passivation. A tiny 0.003–0.005" top chamfer (if geometry allows) pushes any stragglers into the slot — burrs hate commitment. What stickout and coolant pressure are you running?
I killed burrs on Ti‑6Al‑4V slots by adding tiny dog‑bones at each end and doing a full‑depth finish that enters/exits through the reliefs, so the tool never breaks out on the wall — “don’t break out; break in.” Keep the finisher razor‑sharp and run that pass dry or mist-only to avoid smearing; if you have to use coolant, shut it off for the last 0.050" before the relief. What slot width and axial depth are you running?
That tiny hone + SFM nudge on PEEK mirrors what finally made our bag-out tolerable. @alexander_and67’s light finish idea plus a 1–2° tool tilt (5‑axis) and a micro‑chamfered 4‑flute AlTiN, then a 0.0008 in top “crest” pass, rolled the burr inward on titanium and left a surface that passivated clean without hand work. Can you tilt the head, or are you stuck 3‑axis?
On Grade 5 slots, push IPT just above minimum chip thickness and use a stub 3‑flute with about 0.005" corner radius, then add a 0.002" top‑edge kiss‑chamfer in‑process to collapse burrs — like folding the foil edge before tearing — and it still plays nice with ASTM F86 cleaning. Small caveat: keep coolant low‑sulfur/low‑chloride around 6–7% so you don’t carry a film into passivation. @alexander_and67 have you tried a same‑tool helical skim exit to avoid a straight breakout?